Active device substrate

ABSTRACT

A manufacturing method of a crystallized metal oxide layer includes: providing a substrate; forming a first insulation layer on the substrate; forming a first metal oxide layer on the first insulation layer; forming a second metal oxide layer on the first insulation layer; forming a second insulation layer on the first metal oxide layer and the second metal oxide layer; forming a silicon layer on the second insulation layer; performing a first laser process on a portion of the silicon layer covering the first metal oxide layer; and performing a second laser process on a portion of the silicon layer covering the second metal oxide layer. An active device and a manufacturing method thereof are also provided.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a divisional application of and claims the prioritybenefit of a prior application Ser. No. 16/368,891, filed on Mar. 29,2019, now allowed, which claims the priority benefit of Taiwanapplication Ser. No. 107111052, filed on Mar. 29, 2018. The entirety ofeach of the above-mentioned patent applications is hereby incorporatedby reference herein and made a part of this specification.

BACKGROUND OF THE INVENTION Field of the Invention

The invention relates to a crystallized metal oxide layer, and moreparticularly, to a manufacturing method of a crystallized metal oxidelayer, a manufacturing method of an active device substrate, and anactive device substrate.

Description of Related Art

In recent years, due to advances in semiconductor manufacturingtechniques, the manufacturing process of the thin-film transistor (TFT)tends to be simple and fast. As a result, the TFT is extensively appliedin products such as computer chips, mobile phone chips, and liquidcrystal displays (LCDs).

In some products having a thin-film transistor, metal oxide is used as amaterial for the semiconductor channel layer. However, metal oxideformed by a deposition process is often in an amorphous state, andmanufacturing issues readily occur. Therefore, a method for solving theabove issues is urgently needed.

SUMMARY OF THE INVENTION

The invention provides a manufacturing method of a crystallized metaloxide layer in which an amorphous metal oxide layer can be convertedinto a crystallized metal oxide layer using laser.

The invention provides a manufacturing method of an active devicesubstrate in which an amorphous metal oxide layer can be converted intoa crystallized metal oxide layer using laser.

The invention provides an active device substrate that can alleviate theissue of leakage current.

A manufacturing method of a crystallized metal oxide layer of theinvention includes the following. A substrate is provided. A firstinsulation layer is formed on the substrate. A first metal oxide layeris formed on the first insulation layer. A second metal oxide layer isformed on the first insulation layer. A second insulation layer isformed on the first metal oxide layer and the second metal oxide layer,and the first metal oxide layer and the second metal oxide layer arelocated between the first insulation layer and the second insulationlayer. A silicon layer is formed on the second insulation layer, and thesilicon layer covers the first metal oxide layer and the second metaloxide layer. A first laser process is performed on a portion of thesilicon layer covering the first metal oxide layer such that the firstmetal oxide layer is converted into a first crystallized metal oxidelayer. A second laser process is performed on a portion of the siliconlayer covering the second metal oxide layer such that the second metaloxide layer is converted into a second crystallized metal oxide layer.

A manufacturing method of the active device substrate of the inventionincludes the following. A crystallized metal oxide layer is formed viathe method above. A first gate and a second gate are formed on asubstrate. A portion of the silicon layer covering the firstcrystallized metal oxide layer is removed. A first source, a secondsource, a first drain, and a second drain are formed, the first sourceand the first drain are electrically connected to the first crystallizedmetal oxide layer, and the second source and the second drain areelectrically connected to the second crystallized metal oxide layer.

An active device substrate of the invention includes a substrate, afirst insulation layer, a second insulation layer, a first activedevice, a second active device, and a third active device. The substratehas an active region and a peripheral region. The first insulation layeris located on the substrate. The second insulation layer is located onthe first insulation layer. The first active device is located on theactive region, and the first active device includes a first crystallizedmetal oxide layer. The second active device is located on the peripheralregion. The second active device includes a second crystallized metaloxide layer. The first crystallized metal oxide layer and the secondcrystallized metal oxide layer are both in contact with the firstinsulation layer. The third active device is located on the peripheralregion and electrically connected to the second active device. The thirdactive device includes a P-type doped silicon semiconductor layer,wherein the second insulation layer is located between the siliconsemiconductor layer and the first insulation layer.

In order to make the aforementioned features and advantages of thedisclosure more comprehensible, embodiments accompanied with figures aredescribed in detail below.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are included to provide a furtherunderstanding of the invention, and are incorporated in and constitute apart of this specification. The drawings illustrate embodiments of theinvention and, together with the description, serve to explain theprinciples of the invention.

FIG. 1A to FIG. 1E are cross sections of a manufacturing method of acrystallized metal oxide layer according to an embodiment of theinvention.

FIG. 2 is a top view of an active device substrate according to anembodiment of the invention.

FIG. 3A to FIG. 3E are cross sections of a manufacturing method of anactive device substrate according to an embodiment of the invention.

FIG. 4 is a cross section of an active device substrate according to anembodiment of the invention.

FIG. 5 is a cross section of an active device substrate according to anembodiment of the invention.

FIG. 6 is a cross section of an active device substrate according to anembodiment of the invention.

DESCRIPTION OF THE EMBODIMENTS

FIG. 1A to FIG. 1E are cross sections of a manufacturing method of acrystallized metal oxide layer according to an embodiment of theinvention.

Referring first to FIG. 1, a substrate 100 is provided. The material ofthe substrate 100 can be glass, quartz, organic polymer, or anopaque/reflective material (such as conductive material, metal, wafer,ceramic, or other suitable materials), or other suitable materials. If aconductive material or metal is used, then an insulation layer (notshown) is provided on the substrate 100 to prevent short circuits.

A first insulation layer 110 is formed on the substrate 100. Thematerial of the first insulation layer 110 includes, for instance,silicon oxide. In some embodiments, the method of forming the firstinsulation layer 110 includes chemical vapor deposition (CVD) or othersimilar processes.

In some embodiments, other conductive layers can be optionally providedbetween the first insulation layer 110 and the substrate 100, such asmetal, semiconductor, or a combination thereof.

Referring to FIG. 1B, a first metal oxide layer 120 is formed on thefirst insulation layer 110. In some embodiments, the method of formingthe first metal oxide layer 120 includes, for instance, sputtering orother similar processes. In some embodiments, the sputtering process is,for instance, performed at room temperature. The location and shape ofthe first metal oxide layer 120 are, for instance, defined by alithography process. The first metal oxide layer 120 includes, forinstance, an indium element, gallium element, zinc element, and oxygenelement. The first metal oxide layer 120 is, for instance, indiumgallium zinc oxide. In some embodiments, the first metal oxide layer 120includes amorphous metal oxide.

In some embodiments, the thickness of the first insulation layer 110between the first metal oxide layer 120 and the substrate 100 ispreferably 50 nm to 300 nm, such as 100 nm, 150 nm, 200 nm, or 250 nm.Within this thickness range, the first insulation layer 110 can obtainbetter insulation and heat transfer effect. The thickness of the firstmetal oxide layer 120 is preferably, for instance, 10 nm to 120 nm, suchas 20 nm, 40 nm, 60 nm, 80 nm, or 100 nm.

Referring to FIG. 1C, a second metal oxide layer 130 is formed on thefirst insulation layer 110. In some embodiments, the method of formingthe second metal oxide layer 130 includes sputtering or other similarprocesses. In some embodiments, the sputtering process is, for instance,performed at room temperature. The location and shape of the secondmetal oxide layer 130 are, for instance, defined by a lithographyprocess. The second metal oxide layer 130 includes, for instance, anindium element, gallium element, tin element, and oxygen element. Thesecond metal oxide layer 130 is, for instance, indium gallium tin oxide.In some embodiments, the second metal oxide layer 130 includes amorphousmetal oxide.

In some embodiments, the thickness of the first insulation layer 110between the second metal oxide layer 130 and the substrate 100 ispreferably 50 nm to 300 nm, such as 100 nm, 150 nm, 200 nm, or 250 nm.Within this thickness range, the first insulation layer 110 can obtainbetter insulation and heat transfer effect. The thickness of the secondmetal oxide layer 130 is preferably, for instance, 10 nm to 120 nm, suchas 20 nm, 40 nm, 60 nm, 80 nm, or 100 nm.

Referring to FIG. 1D, a second insulation layer 140 is formed on thefirst metal oxide layer 120 and the second metal oxide layer 130. Thefirst metal oxide layer 120 and the second metal oxide layer 130 arelocated between the first insulation layer 110 and the second insulationlayer 140. In the present embodiment, a portion of the second insulationlayer 140 is formed on the first insulation layer 110 and in contactwith the first insulation layer 110.

The material of the second insulation layer 140 includes, for instance,silicon oxide. In some embodiments, the method of forming the secondinsulation layer 140 includes chemical vapor deposition (CVD) or othersimilar processes.

A silicon layer 150 is formed on the second insulation layer 140. Thesilicon layer 150 covers the first metal oxide layer 120 and the secondmetal oxide layer 130. The first insulation layer 110, the first metaloxide layer 120, the second insulation layer 140, and the silicon layer150 are stacked in order in a direction DT perpendicular to thesubstrate 100. The first insulation layer 110, the second metal oxidelayer 130, the second insulation layer 140, and the silicon layer 150are stacked in order in the direction DT perpendicular to the substrate100. In some embodiments, the second insulation layer 140 can preventthe silicon layer 150 from peeling off of the first metal oxide layer120 and the second metal oxide layer 130.

The thickness of the silicon layer 150 is preferably 40 nm to 60 nm,such as 50 nm. In some embodiments, the method of forming the siliconlayer 150 includes CVD or other similar processes. In some embodiments,the silicon layer 150 includes amorphous silicon.

Referring to FIG. 1E, a first laser process L1 is performed on a portionof the silicon layer 150 covering the first metal oxide layer 120 toconvert the first metal oxide layer 120 into a first crystallized metaloxide layer 120′. In some embodiments, the energy of the first laserprocess L1 is 70 mJ/cm² to 500 mJ/cm², such as 100 mJ/cm², 150 mJ/cm²,160 mJ/cm², 200 mJ/cm², 250 mJ/cm², 300 mJ/cm², 350 mJ/cm², 400 mJ/cm²,or 450 mJ/cm². In some embodiments, the first crystallized metal oxidelayer 120′ includes an indium element, gallium element, zinc element,and oxygen element, and the first crystallized metal oxide layer 120′is, for instance, indium gallium zinc oxide.

A second laser process L2 is performed on a portion of the silicon layer150 covering the second metal oxide layer 130 to convert the secondmetal oxide layer 130 into a second crystallized metal oxide layer 130′.In some embodiments, the energy of the second laser process L2 is 70mJ/cm² to 500 mJ/cm², such as 100 mJ/cm², 150 mJ/cm², 160 mJ/cm², 200mJ/cm², 250 mJ/cm², 300 mJ/cm², 350 mJ/cm², 400 mJ/cm², or 450 mJ/cm².In some embodiments, the second crystallized metal oxide layer 130′includes an indium element, gallium element, tin element, and oxygenelement, and the second crystallized metal oxide layer 130′ is, forinstance, indium gallium tin oxide.

In the present embodiment, the first metal oxide layer 120 and thesecond metal oxide layer 130 are both clamped between the firstinsulation layer 110 and the second insulation layer 140, and thereforethe energy needed for the first laser process L1 and the second laserprocess L2 can be reduced.

After the first laser process L1 and the second laser process L2 areperformed, the silicon layer 150 is converted into a silicon layer 150′,and in some embodiments, a portion of the silicon layer 150′ containspolycrystalline silicon, but the invention is not limited thereto. Insome embodiments, the silicon layer 150′ does not containpolycrystalline silicon, and the silicon layer 150 and the silicon layer150′ both contain amorphous silicon.

In some embodiments, the laser used in the first laser process L1 andthe second laser process L2 is excimer laser, blue laser, or greenlaser, and the adopted wavelength is close to the absorption wavelengthof amorphous silicon such that the silicon layer 150 can be moreeffectively heated. The absorption wavelength of the silicon layer 150is about 350 nm to 750 nm. In some embodiments, excimer laser is adoptedto irradiate the silicon layer 150, that is, an excimer laser annealing(ELA) technique is used to process amorphous silicon. In someembodiments, before the silicon layer 150 is irradiated with laser,rapid thermal processing (RTP) is further used to process the siliconlayer 150 to prevent the occurrence of hydrogen explosion.

Based on the above, the first metal oxide layer 120 and the second metaloxide layer 130 are crystallized using a laser process, and thetemperature is low in comparison to the temperature needed for a regularhigh-temperature furnace annealing process. Since the first metal oxidelayer 120 and the second metal oxide layer 130 do not need to becrystallized in a high-temperature furnace annealing manner, each layeron the substrate 100 is less readily peeled off due to coefficient ofthermal expansion mismatch. Moreover, the crystallization of the firstmetal oxide layer 130 and the second metal oxide layer 150 using a laserprocess has a lower temperature than an excimer laser annealing processin a regular high-temperature annealing process.

FIG. 2 is a top view of an active device substrate according to anembodiment of the invention. It should be mentioned here that, theembodiment of FIG. 2 adopts the reference numerals of the embodiment ofFIG. 1A to FIG. 1E and a portion of the contents thereof, wherein thesame or similar numerals are used to represent the same or similardevices and descriptions of the same technical contents are omitted. Theomitted portions are as described in the above embodiments and are notrepeated herein.

Referring to FIG. 2, the active device substrate 10 includes a substrate100, a peripheral circuit DR1, a peripheral circuit DR2, a scan line SL,a data line DL, and a pixel structure PX.

The substrate 100 has an active region AA and a peripheral region BA.The peripheral circuit DR1 and the peripheral circuit DR2 are located onthe peripheral region BA. The scan line SL, the data line DL, and thepixel structure PX are located on the active region AA. The scan line SLand the data line DL are respectively extended onto the active region AAfrom the peripheral circuit DR1 and the peripheral circuit DR2. Each ofthe pixel structures PX is electrically connected to at least one scanline SL. Each of the pixel structures PX is electrically connected to atleast one data line DL.

FIG. 3A to FIG. 3E are cross sections of a manufacturing method of anactive device substrate according to an embodiment of the invention. Itshould be mentioned here that, the embodiment of FIG. 3A to FIG. 3Eadopts the reference numerals of the embodiment of FIG. 2 and a portionof the contents thereof, wherein the same or similar numerals are usedto represent the same or similar devices and descriptions of the sametechnical contents are omitted. The omitted portions are as described inthe above embodiments and are not repeated herein.

FIG. 3A is, for instance, a subsequent process to FIG. 1E. Referring toFIG. 3A, a silicon layer 150′ includes amorphous silicon, and a thirdlaser process L3 is performed on the silicon layer 150′ to form asilicon layer 150 a including polycrystalline silicon. The silicon layer150 a, the first crystallized metal oxide layer 120′, and the secondcrystallized metal oxide layer 130′ are not overlapped in the directionDT perpendicular to the substrate 100.

Referring to FIG. 3B, a portion of the silicon layer 150′ covering thefirst crystallized metal oxide layer 120′ is removed. A portion of thesilicon layer 150′ covering the second crystallized metal oxide layer130′ is removed. In some embodiments, all of the remaining silicon layer150′ is removed to only leave the silicon layer 150 a.

A first gate G1 and a second gate G2 are formed on the substrate 100,and the first gate G1 and the second gate G2 are separated from eachother. The material of the first gate G1 and the second gate G2includes, for instance, silver, aluminum, copper, molybdenum, titanium,gold, other conductive materials, or a combination of the conductivematerials. The first gate G1 and the second gate G2 are, for instance,formed at the same time, and the forming method of the first gate G1 andthe second gate G2 includes, for instance, a deposition process,lithography process, and other suitable processes. In some embodiments,the first gate G1 is, for instance, electrically connected to the scanline SL (shown in FIG. 2). In some embodiments, the first gate G1, thesecond gate G2, and the scan line SL are formed in the same process.

In the present embodiment, the second insulation layer 140 is locatedbetween the first gate G1 and the first crystallized metal oxide layer120′ and between the second gate G2 and the second crystallized metaloxide layer 130′. The first gate G1 and the first crystallized metaloxide layer 120′ are overlapped in the direction DT perpendicular to thesubstrate 100, and the second gate G2 and the second crystallized metaloxide layer 130′ are overlapped in the direction DT perpendicular to thesubstrate 100.

Referring to both FIG. 3B and FIG. 3C, a third insulation layer 160 isformed on the first gate G1, the second gate G2, the silicon layer 150a, and the second insulation layer 140. The material of the thirdinsulation layer 160 includes, for instance, silicon oxide, siliconnitride, silicon oxynitride, a polymer material, or other suitablematerials. The method of forming the third insulation layer 160includes, for instance, CVD, coating, or other similar processes.

A third gate G3 is formed on the third insulation layer 160, and thethird gate G3 and the silicon layer 150 a are overlapped in thedirection DT perpendicular to the substrate 100. The material of thethird gate G3 includes, for instance, silver, aluminum, copper,molybdenum, titanium, gold, other conductive materials, or a combinationof the conductive materials. The forming method of the third gate G3includes, for instance, a deposition process, lithography process, andother suitable processes. In the present embodiment, although the firstgate G1 and the second gate G2 are formed on the second insulation layer140 and located between the second insulation layer 140 and the thirdinsulation layer 160, the invention is not limited thereto. In otherembodiments, the first gate G1 and the second gate G2 are both formed onthe third insulation layer 160.

A fourth insulation layer 170 is formed on the third gate G3 and thethird insulation layer 160. The material of the fourth insulation layer170 includes, for instance, silicon oxide, silicon nitride, siliconoxynitride, a polymer material, or other suitable materials. The methodof forming the fourth insulation layer 170 includes, for instance, CVD,coating, or other similar processes.

A doping process is performed on the silicon layer 150 a to form asilicon semiconductor layer 150 b. The doped silicon semiconductor layer150 b includes a source region 152, a channel region 154, and a drainregion 156, and the channel region 154 is located between the sourceregion 152 and the drain region 156. The source region 152 and the drainregion 156 include, for instance, a P-type semiconductor. In the presentembodiment, the doping process performed on the silicon semiconductorlayer 150 b is performed after the third gate G3 is formed. Forinstance, the doping process is performed on the silicon layer 150 awith the third insulation layer 160 in between, but the invention is notlimited thereto. In other embodiments, the doping process can also beperformed before the third gate G3 is formed. For instance, a photomaskis formed on the silicon layer 150 a, and then a doping process isperformed on the silicon layer 150 a.

Referring to FIG. 3C and FIG. 3D, a plurality of openings is formed inthe second insulation layer 140, the third insulation layer 160, and thefourth insulation layer 170. The first source S1, the first drain D1,the second source S2, the second drain D2, the third source S3, and thethird drain D3 are formed on the fourth insulation layer 170. The firstsource S1, the first drain D1, the second source S2, the second drainD2, the third source S3, and the third drain D3 are respectively filledin the corresponding openings. The first source S1 and the first drainD1 are electrically connected to the first crystallized metal oxidelayer 120′. The second source S2 and the second drain D2 areelectrically connected to the second crystallized metal oxide layer130′. The third source S3 and the third drain D3 are respectivelyelectrically connected to the source region 152 and the drain region 156of the silicon semiconductor layer 150 b. At this point, the firstactive device T1, the second active device T2, and the third activedevice T3 are largely complete. In the present embodiment, the firstactive device T1, the second active device T2, and the third activedevice T3 all include a top gate active device, but the invention is notlimited thereto. In other embodiments, the first active device T1, thesecond active device T2, and the third active device T3 can also bebottom gate active devices.

The second active device T2 and the third active device T3 are, forinstance, located on the peripheral region BA (shown in FIG. 2) of thesubstrate 100. The second active device T2 and the third active deviceT3 are, for instance, a portion of the peripheral circuit DR1 (shown inFIG. 2) or the peripheral circuit DR2 (shown in FIG. 2), and can be usedas, for instance, the active devices in a multiplexer, driver circuit,or other electronic devices. The first active device T1 is, forinstance, located on the active region AA (shown in FIG. 2) of thesubstrate 100. The first active device T1 is, for instance (shown inFIG. 2), a portion of the pixel structure PX.

In some embodiments, the first source S1 of the first active device T1is electrically connected to the data line DL (shown in FIG. 2). In someembodiments, the first source S1, the first drain D1, the second sourceS2, the second drain D2, the third source S3, the third drain D3, andthe data line DL are formed in the same process.

In some embodiments, one of the third source S3 and the third drain D3of the third active device T3 is electrically connected to one of thesecond source S2 and the second drain D2 of the second active device T2.The third source S3 or the third drain D3 of the third active device T3is electrically connected to the second crystallized metal oxide layer130′ of the second active device T2. The invention is not limited to thethird drain D3 being electrically connected to the second source S2.

In some embodiments, the second crystallized metal oxide layer 130′ isan intrinsic semiconductor, and has free electrons as carriers withoutrequiring a doping process (for instance, electrons are transferred byoxygen vacancies). Therefore, the third active device T3 having a P-typeconductivity channel layer and the second active device T2 having anN-type conductivity channel layer can be combined into a complementarymetal-oxide-semiconductor (CMOS). The beneficial effect of power savingcan be obtained without an additional N-type doping process.

Referring to FIG. 3E, a planarization layer electrode formed on thefirst source S1, the first drain D1, the second source S2, the seconddrain D2, the third source S3, and the third drain D3. The planarizationlayer 180 is at least located on the active region AA of the substrate100. A pixel electrode PE is formed on the planarization layer 180. Theplanarization layer 180 has a plurality of openings, and the pixelelectrode PE is filled in the openings of the planarization layer 180and electrically connected to the first drain D1.

In the present embodiment, an active device substrate 20 includes asubstrate 100, a first insulation layer 110, a second insulation layer140, a first active device T1, a second active device T2, and a thirdactive device T3. The substrate 100 has an active region AA and aperipheral region BA. The first insulation layer 110 is located on thesubstrate 100. The second insulation layer 140 is located on the firstinsulation layer 110. The first active device T1 is located on theactive region AA, and the first active device T1 includes a firstcrystallized metal oxide layer 120′. The second active device T2 islocated on the peripheral region BA. The second active device T2includes a second crystallized metal oxide layer 130′. The firstcrystallized metal oxide layer 120′ and the second crystallized metaloxide layer 130′ are both in contact with the first insulation layer110. The third active device T3 is located on the peripheral region BAand electrically connected to the second active device T2. The thirdactive device T3 includes a P-type doped silicon semiconductor layer 150b, wherein the second insulation layer 140 is located between thesilicon semiconductor layer 150 b and the first insulation layer 110.

In the present embodiment, the first crystallized metal oxide layer 120′of the first active device T1 is, for instance, indium gallium zincoxide, and therefore the pixel structure PX (shown in FIG. 2) can havethe properties of low frame rate and low Ioff.

In the present embodiment, the second crystallized metal oxide layer130′ of the second active device T2 is, for instance, indium galliumzinc oxide or indium gallium tin oxide, and can be combined with thethird active device T3 containing the P-type doped silicon semiconductorlayer 150 b into a CMOS to increase the current efficiency of the activedevice substrate.

FIG. 4 is a cross section of an active device substrate according to anembodiment of the invention. It should be mentioned here that, theembodiment of FIG. 4 adopts the reference numerals of the embodiment ofFIG. 3A to FIG. 3E and a portion of the contents thereof, wherein thesame or similar numerals are used to represent the same or similardevices and descriptions of the same technical contents are omitted. Theomitted portions are as described in the above embodiments and are notrepeated herein.

The difference between an active device substrate 30 of the embodimentof FIG. 4 and the active device substrate 20 of the embodiment of FIG.3E is that in the active device substrate 30, the first gate G1 and thesecond gate G2 are formed on the substrate 100 before the firstinsulation layer 110 is formed on the substrate 100.

The first gate G1 and the first crystallized metal oxide layer 120′ areoverlapped in the direction DT perpendicular to the substrate 100, andthe second gate G2 and the second crystallized metal oxide layer 130′are overlapped in the direction DT perpendicular to the substrate 100.In the present embodiment, the first active device T1 and the secondactive device T2 include a bottom gate active device.

In some embodiments, the first gate G1 and the second gate G2 locatedbelow the first crystallized metal oxide layer 120′ and the secondcrystallized metal oxide layer 130′ have good heat conduction function,and the crystal quality of the first crystallized metal oxide layer 120′and the second crystallized metal oxide layer 130′ can be increased whenthe first laser process and the second laser process are performed.

FIG. 5 is a cross section of an active device substrate according to anembodiment of the invention. It should be mentioned here that, theembodiment of FIG. 5 adopts the reference numerals of the embodiment ofFIG. 4 and a portion of the contents thereof, wherein the same orsimilar numerals are used to represent the same or similar devices anddescriptions of the same technical contents are omitted. The omittedportions are as described in the above embodiments and are not repeatedherein.

The difference between an active device substrate 40 of the embodimentof FIG. 5 and the active device substrate 30 of the embodiment of FIG. 4is that in the active device substrate 40, the silicon semiconductorlayer 150 b is located between the second crystallized metal oxide layer130′ and the third gate G3.

In some embodiments, the circuit diagrams of the second active device T2and the third active device T3 are similar to the circuit diagrams ofthe second active device T2 and the third active device T3 in theembodiment of FIG. 4. In other words, the second source S2 or the seconddrain D2 is electrically connected to the second crystallized metaloxide layer 130′ of the second active device T2 and the siliconsemiconductor layer 150 b of the third active device T3, but theinvention is not limited thereto. One of the second source S2 and thesecond drain D2 is electrically connected to the silicon semiconductorlayer 150 b, and one of the third source S3 and the third drain D3 iselectrically connected to the second crystallized metal oxide layer130′. For instance, one of the second source S2 and the second drain D2is electrically connected to one of the third source S3 (blocked by thesecond source S2 in FIG. 5) and the third drain D3 (blocked by thesecond drain S2 in FIG. 5).

In the present embodiment, the silicon semiconductor layer 150 b and thesecond crystallized metal oxide layer 130′ are overlapped in thedirection DT perpendicular to the substrate 100. In some embodiments,when the second metal oxide layer is converted into the secondcrystallized metal oxide layer 130′ in the second laser process,amorphous silicon in the silicon layer on the second crystallized metaloxide layer 130′ is converted into polycrystalline silicon, andtherefore the cost of the third laser process can be reduced.

In the present embodiment, the second active device T2 and the thirdactive device T3 located in the peripheral region BA are overlapped, andtherefore the border width of the active device substrate can bereduced.

FIG. 6 is a cross section of an active device substrate according to anembodiment of the invention. It should be mentioned here that, theembodiment of FIG. 6 adopts the reference numerals of the embodiment ofFIG. 4 and a portion of the contents thereof, wherein the same orsimilar numerals are used to represent the same or similar devices anddescriptions of the same technical contents are omitted. The omittedportions are as described in the above embodiments and are not repeatedherein.

The difference between an active device substrate 50 of the embodimentof FIG. 6 and the active device substrate 30 of the embodiment of FIG. 4is that in the active device substrate 50, the third gate G3 is locatedbetween the first insulation layer 110 and the substrate 100.

In the present embodiment, before the first insulation layer 110 isformed, the first gate G1, the second gate G2, and the third gate G3 areformed. The first gate G1, the second gate G2, and the third gate G3are, for instance, formed in the same process.

In the present embodiment, the second insulation layer 140 located onthe first crystallized metal oxide layer 120′ and the secondcrystallized metal oxide layer 130′ is removed, and a portion of thesecond insulation layer 140 located between the silicon semiconductorlayer 150 b and the first insulation layer 110 is left.

The first source S1, the first drain D1, the second source S2, thesecond drain D2, the third source S3, and the third drain D3 are formed.The method of forming the first source S1, the first drain D1, thesecond source S2, the second drain D2, the third source S3, and thethird drain D3 includes, for instance, first depositing an entireconductive layer M and then patterning the conductive layer M to form aplurality of openings H.

In some embodiments, the crystallized metal oxide layer has betteranti-etching ability than the amorphous metal oxide layer, and thereforedamage caused by an etchant to the first crystallized metal oxide layer120′ and the second crystallized metal oxide layer 130′ when theconductive layer M is patterned can be reduced. In some embodiments,oxalic acid, aluminate, hydrofluoric acid, or other similar etchants isused in the patterning of the conductive layer M. In some embodiments,the conductive layer M adopts a molybdenum-aluminum-molybdenummultilayer structure having lower resistance and lower manufacturingcost, and aluminate etchant can be used when the conductive layer M ispatterned to further reduce manufacturing cost.

In at least one embodiment of the invention, the cost for formingdifferent crystallized metal oxide layers can be reduced. In at leastone embodiment of the invention, the leakage current issue of the activedevice substrate can be alleviated. In at least one embodiment of theinvention, the current efficiency of the active device substrate can beincreased. In at least one embodiment of the invention, the border widthof the active device substrate can be reduced.

Although the invention has been described with reference to the aboveembodiments, it will be apparent to one of ordinary skill in the artthat modifications to the described embodiments may be made withoutdeparting from the spirit of the invention. Accordingly, the scope ofthe invention is defined by the attached claims not by the abovedetailed descriptions.

What is claimed is:
 1. An active device substrate, comprising asubstrate having an active region and a peripheral region; a firstinsulation layer located on the substrate; a second insulation layerlocated on the first insulation layer; a first active device located onthe active region, wherein the first active device comprises a firstcrystallized metal oxide layer; a second active device located on theperipheral region, wherein the second active device comprises a secondcrystallized metal oxide layer, and the first crystallized metal oxidelayer and the second crystallized metal oxide layer are both in contactwith the first insulation layer; and a third active device located onthe peripheral region and electrically connected to the second activedevice, wherein the third active device comprises a P-type doped siliconsemiconductor layer, and the second insulation layer is located betweenthe P-type doped silicon semiconductor layer and the first insulationlayer.
 2. The active device substrate of claim 1, wherein the firstactive device comprises: a first gate overlapped with the firstcrystallized metal oxide layer in a direction perpendicular to thesubstrate, and a first source and a first drain electrically connectedto the first crystallized metal oxide layer; and the second activedevice comprises: a second gate overlapped with the second crystallizedmetal oxide layer in the direction perpendicular to the substrate, and asecond source and a second drain electrically connected to the secondcrystallized metal oxide layer.
 3. The active device substrate of claim2, further comprises: a third insulation layer, disposed on and incontact with a top surface of the first gate, a top surface of thesecond gate, and a top surface of the P-type doped silicon semiconductorlayer, wherein the third insulation layer is located between a thirdgate of the third active device and the P-type doped silicon.
 4. Theactive device substrate of claim 2, wherein: the third active devicecomprises a third gate, and the P-type doped silicon semiconductor layeris located between the second crystallized metal oxide layer and thethird gate.
 5. The active device substrate of claim 4, wherein theP-type doped silicon semiconductor layer and the second crystallizedmetal oxide layer are located between the third gate and the secondgate.
 6. The active device substrate of claim 1, wherein the P-typedoped silicon semiconductor layer and the second crystallized metaloxide layer are overlapped in a direction perpendicular to thesubstrate.
 7. The active device substrate of claim 1, wherein the firstcrystallized metal oxide layer comprises an indium element, a galliumelement, a zinc element, and an oxygen element, and the secondcrystallized metal oxide layer comprises an indium element, a galliumelement, a tin element, and an oxygen element.
 8. The active devicesubstrate of claim 1, wherein a material of the first insulation layerand the second insulation layer comprises silicon oxide.
 9. The activedevice substrate of claim 1, wherein a material of the firstcrystallized metal oxide layer is different material with a material ofthe second crystallized metal oxide layer, a bottom surface of the firstcrystallized metal oxide layer and a bottom surface of the secondcrystallized metal oxide layer are in contact with the first insulationlayer.
 10. The active device substrate of claim 9, wherein a top surfaceof the first crystallized metal oxide layer and a top surface of thesecond crystallized metal oxide layer are in contact with the secondinsulation layer.
 11. The active device substrate of claim 10, wherein abottom surface of the P-type doped silicon semiconductor layer is incontact with the second insulation layer.
 12. The active devicesubstrate of claim 1, wherein the second insulation layer is a patternedlayer which is not overlapping the first active device and the secondactive device in a direction perpendicular to the substrate.
 13. Theactive device substrate of claim 12, wherein: the third active devicecomprises a third source and a third drain connected with sidewalls ofthe second insulation layer and sidewalls of the P-type doped siliconsemiconductor layer.
 14. The active device substrate of claim 1, whereinthe first crystallized metal oxide layer and the second crystallizedmetal oxide layer are crystallized using a laser process.
 15. The activedevice substrate of claim 14, wherein the first crystallized metal oxidelayer and the second crystallized metal oxide layer are both clampedbetween the first insulation layer and the second insulation layer, andwherein the first insulation layer and the second insulation layer areconfigured as heat preservation layers in the laser process.